Ripple-carry adder, Manchester carry chain adder Bit-Serial or bit-parallel Bit-serial, bit-parallel (nearly all others) Processing location Near memory, in memory (all others) Cache-level where PIM is implemented Private L1 cache, uppermost cache-level where all operands are present, LLC Nature of computation Analog Analog (voltage), Analog (time) Digital Whether multiple rows or columns are selected for parallel processing Multi row Multi column Whether only circuit-level or end-to-end evaluation of SRAM-PIM is done Only circuit-level End-to-end evaluation References Circuit-design related Differential design/operation Differential SA, differential read, differential averaging Discharge-related optimizations selecting the resistance of the transmission gate to control the discharge profiles of the three BLs, controlling the discharge speed according to the bit-significance Bit weighting by using digital barrel shifting, transistor-sizing, by adapting the discharge speed Voltage divider scheme to realize "implication" and XOR gates and XNOR gate Reducing circuit complexity avoiding the need of SA since the kernel itself acts as a SA, avoiding the need of ADC by using a comparator circuit Sizing strategies.
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